1. Field of the Invention
The present invention relates to semiconductor fabrication.
2. Description of the Related Art
During copper interconnect manufacturing, a copper layer is deposited on a seed/barrier layer using an electroplating process. Components in the electroplating solution provide for appropriate gap fill on sub-micron features. However, these sub-micron features tend to plate faster than the bulk areas and larger, i.e., greater than 1 micrometer, trench regions. The sub-micron regions are typically found in large memory arrays such as, for example, static random access memory (SRAM), and can span large areas of the wafer. It should be appreciated that this causes large areas of the wafer to have additional topography that needs to be planarized, in addition to the larger trench regions that also need to be planarized.
FIG. 1 is a simplified schematic diagram illustrating a silicon substrate having a copper layer deposited thereon. A copper layer 103 is deposited on a seed/barrier layer disposed over silicon wafer 101 using an electroplating process. As previously mentioned, components in the electroplating solution provide for good gap fill on sub-micron features, such as sub-micron trenches in region 105, but these features tend to plate faster than the bulk areas and trench regions 107 and 109. High regions or “steps” in the topography of the substrate, illustrated by region 111, result over the sub-micron trench region 105. These steps are also referred to as “superfill” regions. The superfill region 111 is defined by thicker copper film than field regions 108 and trench regions 107 and 109. The superfill regions 111 must be planarized along with the topography over the field regions 108 and trench regions 107 and 109.
Current planarization techniques are not suited to handle the superfill topography in an efficient manner, i.e., planarization techniques are sensitive to pattern density and circuit layout. More specifically, chemical mechanical planarization (CMP) processes often must be tuned according to the incoming wafer properties. Therefore, changes are made to the CMP process (such as changing step times, overpolish time, or endpoint algorithms, for example) in order to accommodate variations within or between wafer lots. Also, such changes are made to the CMP process to accommodate different pattern densities and circuit layouts encountered on wafers of mixed-product manufacturing lines.
When attempting to perform a single CMP process on the topography having superfill regions, excessive dishing and erosion can occur in trench regions 107 and 109 when overpolishing is performed in order to completely remove the remaining copper from the superfill region 111. Additionally, not only is the CMP process required to remove the excess copper in the region 111, but the CMP process is also required to perform this removal in a manner that follows a contour of the substrate. The contour of the substrate is due to waviness inherent to the silicon substrate. The waviness is typically on the order of 0.2 micrometer to 0.5 micrometer total thickness variation. Current CMP processes do not suitably deal with both superfill region topography and substrate contour, while effectively planarizing the other topography in the trench and field regions. In an ideal case, the copper film to be removed would consist of a uniformly thick conformal film including a homogeneous pattern layout and density.
In view of the foregoing, a solution is needed to effectively and efficiently remove material from a semiconductor wafer having large topographical variations.